1. Field of the Invention
The present invention relates generally to techniques for forming conductive vias of semiconductor device components and, more specifically, to conductive via-forming techniques in which conductive material is selectively deposited on the surfaces of a via hole without being deposited on the major surfaces of the semiconductor device component through which the via extends. The present invention also relates to conductive vias with selectively deposited conductive layers, as well as to semiconductor device components that include the conductive vias and semiconductor device assemblies that include the semiconductor device components.
2. Background of Related Art
The parallel trends of ever-decreasing size and ever-increasing ability in the electronics industry have driven a need for semiconductor devices, semiconductor device assemblies, and semiconductor device packages of ever-decreasing size and ever-increasing feature density. One approach that has been taken to facilitate these trends has been to make as many electrical connections between components as possible in a given amount of “real estate,” or area. This approach is applicable to both adjacent components and non-adjacent components.
Conductive vias have been used to provide electrical pathways between components that are superimposed relative to one another, but that are not directly adjacent to each other. A conductive via, which may be formed through a circuit board, an interposer, or a semiconductor device, provides such an electrical pathway. Conductive vias typically include a hole formed through the substrate, an insulative lining, if the substrate is formed from a semiconductive or conductive material, and a conductive element that passes through the opening, which may be electrically isolated from the substrate by way of the insulative lining. As with most features of semiconductor devices, the dimensions of the various elements of conductive vias also continue to decrease.
U.S. Pat. No. 6,841,883 to Farnworth et al. (hereinafter “Farnworth”), the entire disclosure of which is hereby incorporated herein, in its entirety, by this reference, describes exemplary processes for forming conductive vias through semiconductor device structures. In current state-of-the-art processes for fabricating conductive vias, via holes are lined with materials with low dielectric constants, such as parylene and the fluoropolymer resins (including, but not limited to, polytetrafluoroethylene (“PTFE”), fluorinated ethylenepropylene (“FEP”), ethylene-tetrafluoroethylene (“ETFE”), chlorotrifluoroethylene (“CTFE”), and perfluoroalkoxyalkane (“PFA”), which are marketed by E.I. du Pont de Nemours and Company under the trademark TEFLON®). Although these and similar materials may be used to form very thin insulative coatings on the surfaces of via holes, they do not adhere well to the materials (e.g., silicon) of many substrates through which via holes are formed or to the conductive materials that are subsequently introduced into the via holes to form an electrically conductive via.
The low adhesion of such dielectric materials, as well the potential for misalignment when multiple masks are used to form and passivate via holes may result in shorting between a conductive via and the substrate through which the conductive via extends.
In addition, some of the processes that are currently used to fabricate conductive vias are complex, require expensive materials or equipment that is not widely used in semiconductor device fabrication processes, or are otherwise undesirable.
Accordingly, there are needs for processes for fabricating conductive vias with state-of-the-art dimensions and capabilities while employing common semiconductor device fabrication techniques.